The present invention relates to a nonvolatile semiconductor storage device, and a manufacturing method thereof. More particularly, it relates to a resistance change type nonvolatile semiconductor storage device, and a manufacturing method thereof.
In the field of a nonvolatile memory, active studies have been made on Flash Memory, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), OUM (Ovonic Unified Memory), PRAM (Phase change Random Access Memory; Patent Document 1), and the like.
Recently, there has been proposed a resistance change type nonvolatile memory (ReRAM: Resistance Random Access Memory) different from the nonvolatile memories (Non-Patent Document 1). In the resistance change type nonvolatile memory, information is written by changing the resistance value of the resistance change part of the memory cell by application of a voltage pulse. The resistance change type nonvolatile memory is capable of nondestructive reading of written information. In addition, the resistance change type nonvolatile memory is small in element area, and is capable of value multiplexing. For this reason, the resistance change type nonvolatile memory is regarded promising as having a possibility surpassing those of existing nonvolatile memories.
In order to perform the resistance changing operation of the resistance change type nonvolatile memory with good reproduction, it is necessary to control the current and the voltage applied to the resistance change part (Non-Patent Document 5). Thus, there is proposed a structure in which one transistor and one resistance change part are coupled in series (1T1R structure) (Patent Document 3). With this structure, by controlling the resistance of the transistor with the gate voltage, it is possible to control the current and the voltage to be applied to the resistance change part.
On the other hand, in Patent Document 2 and Patent Document 3, cross-point type PRAM and MRAM are proposed, respectively. The cross-point type memory means, for example, in the case of PRAM, a memory array in which resistance change elements (1D1R structures) each including one diode and one resistance change part coupled in series therein are coupled to respective points of intersection between a plurality of X wires and a plurality of Y wires. By implementing such a 1D1R structure, it is possible to avoid the bypass current generated when the resistance change part is sandwiched between simple grid-like wires by the diode. Further, the transistor for controlling the current and the voltage to be applied to the resistance change element may be desirably formed at each end of the memory array. Therefore, the area of the memory cell may be smaller than that of the 1T1R structure.
ReRAMs include two types of a bipolar operation type and a unipolar operation type (Non-Patent Documents 1 and 2). The unipolar operation type is capable of a unipolar operation. Therefore, the unipolar operation type is advantageous for operating the memory cell of the cross-point type memory including a diode coupled in series therein. The resistance change mechanisms are largely classified into two of the electrochemical type and the filament type. The unipolar operation type is the phenomenon observed only in the filament type ReRAM.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2007-149170[Patent Document 2]    Published Japanese translation of PCT application No. 2005-522045; US Patent No. 2008/0258129(A1)[Patent Document 3]    U.S. Pat. No. 5,640,343[Patent Document 4]    Japanese Unexamined Patent Publication No. 2010-067942; US Patent No. 2010/0038617(A1)[Non-Patent Document 1]    W. W. Zhuang et al., “Novell Colossal Mangetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, Electron Devices Meeting, 2002. IEDM '02. Digest. International, pp. 193-196 (2002).[Non-Patent Document 2]    Shima et al. “Resistance switching in the metal deficient-type oxides: NiO and CoO”, Appl. Phys. Lett. 91, 012901 (2007).[Non-Patent Document 3]    Tsunoda et al., “Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V”, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp. 767-770 (2007).[Non-Patent Document 4]    Y. Sakotsubo et al., “A New Approach for Improving Operating Margin of Unipolar ReRAM Using Local Minimum of Reset Voltage”, 2010 Symposium on VLSI Technology Digest of Technical Papers, pp. 87-88 (2010).[Non-Patent Document 5]    Y. Sasago et al., “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode”, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 24-25 (2009).[Non-Patent Document 6]    J. H. Oh. et al., “Full Integration of Highly Manufacturable 512 Mb PRAM based on 90 nm Technology”, Electron Devices Meeting, 2006. IEDM '06. International, pp. 1-4 (2006).